1. Field of the Invention
The present invention relates to strobed comparator circuits, and in particular, to strobed comparator circuits using regenerative latches.
2. Description of the Related Art
The processing stage of a pipelined analog-to-digital (A/D) converter includes a coarse A/D converter, a digital-to-analog (D/A) converter and a subtractor/gain circuit for calculating the residue to be passed on to the subsequent pipeline stage. The D/A converter and subtractor/gain stages are typically combined into the same switched capacitor circuit. During the sampling phase, the analog value is acquired by the current processing stage. During the hold phase the D/A and subtraction/gain operations are performed. Following the sampling phase and prior to the hold phase a comparison phase occurs since the D/A conversion depends upon the result of such comparison. This comparison is performed by a comparator circuit. Due to the reciprocal nature of the operations of successive stages within the A/D pipeline, the propagation time of the comparator function is effectively subtracted from the time allowed for the hold phase. Hence, in high speed circuits it is important to minimize the comparator propagation time so as to maximize the settling time available during the hold phase of operation.
All signal comparators have a propagation delay which is dependent upon the magnitude of the input signal (e.g., lower delay for a higher magnitude input signal). However, in a pipeline A/D application, a fixed and relatively large delay is associated with the comparison phase so as to allow for the worst case situation of the lowest possible input signal.
Additionally, high speed comparators often suffer from metastability. A metastable state occurs in strobed comparators when the inputs to the comparator are very close to the threshold value. Such metastability cannot be completely avoided. However, some techniques have been developed for reducing the probability of the occurrence of such metastability. One conventional technique involves the use of cascade latching. However, cascade latching cannot be used for high speed pipelined AID converters due to the large comparator propagation time which degrades the high speed performance caused by a reduced settling time.
Accordingly, it would be desirable to have a high speed strobed comparator which further maximizes the available settling time and further minimizes the probability of problems due to metastability.